Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Have you ever released a design, even though you were not fully confident that it was completely verified? Well, you are not alone. The pressure of getting to market faster often results in the ...

To test complex devices, test engineers must rely on the vector sets generated by verification engineers. Unfortunately, verification engineers—who work in a software simulation environment—often have ...

Since the IEEE’s adoption of SystemVerilog as IEEE Standard 1800-2005, and EDA vendors’ subsequent release of products supporting that standard, the semiconductor verification teams my company serves ...

Today, teams often rely on disconnected logs, postmortems, and ad-hoc debug when failures emerge in the field. Lifecycle ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...