Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
Electronic Design

CMOS Circuit Design, Layout, and Simulation, Second Edition

CMOS technology has dominated the IC business for the last 25 years and will continue to do so for another 25 years, according to the author of CMOS Circuit Design, Layout, and Simulation. He explains ...
Semiconductor Engineering

Combining CMOS IC And MEMS Design For IoT Edge Devices

Creating a sensor-based IoT edge device is challenging, due to the multiple design domains involved. But, creating an edge device that combines the electronics using the traditional CMOS IC flow and a ...
EDN

IC Performance: Challenges in Layout with CMOS Technology Nodes

Editor’s note: I am pleased to bring you an important technical blog by Fernando Lavalle, a Ph.D. student at Texas A&M University and his colleague, Suraj Prakash, who have been working and studying ...
EDN

What is Full Custom Layout Design

As we all know, the back-end design of layout implementation known as integrated circuit (IC) layout — is simplistically divided into ASIC-style flow and full-custom flow. This article will try to ...
Semiconductor Engineering

Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)

A new technical paper titled “Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies” was published by researcher at the Technical University of Munich (TUM). “As ...